Semiconductor integrated circuit (IC) technology is continually progressing to circuit layouts having smaller feature sizes as well as increased density. As a result of this continuous progression, photolithography equipment has continually become more expensive and more complex. An electron-beam (or “e-beam”) technique is used to pattern a substrate.
E-beam patterning relates to a process for creating changes in a medium using e-beams. Specifically, some e-beam processes use e-beams to write design patterns onto a resist layer. E-beam patterning provides a way to create features on a substrate where the features are smaller than a resolution limit for light.
However, one issue with e-beam writing is that the resists used for e-beam writing lithography are insulating polymers. Consequently, charges trapped in the resist generate change of the surface potential which deflects incoming electrons and lead to pattern placement error. Currently, the surface potential removal effort is focused mainly on the trapped charge, through conducting layer coating. Treatments on resist such as conducting layer coating or resist thickness adjustment, which essentially disturb the imaging layer, would induce imaging quality degradation and imply more effort on imaging quality optimization.
Therefore, what is needed is a method to address the above issue with improved e-beam patterning performance.